1. Field of the Invention
The present invention relates to readout of a ferroelectric memory device having a single-transistor, single-capacitor (1T1C) memory cell structure.
2. Description of the Prior Art
In ferroelectric memory devices having the 1T1C memory cell structure, it is necessary to generate a reference level to determine whether the data in the memory cell is xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99 when the data is read out. A method of generating the reference level uses a dummy cell. An example of this method is disclosed in Japanese Laid-open Patent Application No. H02-301093. The method disclosed in Japanese Laid-open Patent Application No. H02-301093 will be described with reference to FIG. 14.
FIG. 14 is a circuit diagram of a conventional ferroelectric memory device. The ferroelectric memory device in FIG. 14 comprises a memory cell MC in which data is stored, a dummy cell DMC generating the reference level, and a sense amplifier 10C determining whether the data in the memory cell is xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99. The memory cell MC is selected by a word line WL, and a plate line PL is driven, so that a signal potential is generated on a bit line BL1. The dummy cell DMC is selected by a word line DWL, and a plate line DPL is driven, so that a reference potential is generated on the bit line BL2.
As a ferroelectric capacitor DC of the dummy cell DMC, a capacitor having a smaller size than a ferroelectric capacitor C of the memory cell MC is used. That is, a level intermediate between the levels of the data xe2x80x980xe2x80x99 and the data xe2x80x981xe2x80x99 in the memory cell MC is generated by making the size of the ferroelectric capacitor DC of the dummy cell DMC different from the ferroelectric capacitor C of the memory cell MC. The reference level is adjusted by adjusting the size of the ferroelectric capacitor DC of the dummy cell DMC.
FIG. 14 shows a case where the number of memory cells MC is one. However, in ordinary cases, a plurality of memory cells, for example, 64 to 256 memory cells are connected to the bit line BL1. On the contrary, the number of dummy cells DMC is one.
In the above-described ferroelectric memory device, the generation of the reference level is realized by using a dummy cell.
However, in the conventional ferroelectric memory device, since the number of memory cells MC connected to one bit line is large unlike the number of dummy cells DMC connected to one bit line, the access frequency of the dummy cell is higher than that of the memory cells MC. Consequently, the dummy cell DMC deteriorates soon. The deterioration of the dummy cell DMC changes the reference level from the initially set one to a different one, so that the data in the memory cell MC cannot be read out correctly.
Moreover,in the conventional ferroelectric memory device, it is necessary to write predetermined data into the dummy cell DMC before performing reading, to generate a constant reference level. Since it is necessary to write the same data as the predetermined data every time irrespective of the data in the memory cell MC, a period for writing into the dummy cell DMC is required in addition to the period for writing into the memory cell MC.
Moreover, in the conventional ferroelectric memory device, the capacitor size of the dummy cell DMC is designed so that a level intermediate between the levels of the reading signals xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 of the memory cell MC is generated. However, in this designing of the capacitor size of the dummy cell DMC, it is necessary to previously estimate the levels of the reading signals xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 of the memory cell MC and the levels of the reading signals when the capacitor size is changed to one for the dummy cell DMC. This makes it difficult to design the capacitor size of the dummy cell DMC.
Moreover, in the conventional ferroelectric memory device, the capacitor size of the dummy cell DMC is decided in the design phase, and cannot easily be changed thereafter. This makes it difficult to always ensure a reading operation margin for sample characteristic variations in a case such that the ferroelectric memory device is mass-produced.
An object of the present invention is to provide a high-speed, high-reliability ferroelectric memory device in which the reference level can be generated without the use of a dummy cell.
Another object of the present invention is to provide a ferroelectric memory device in which the reference level is easily designed in the design phase of the ferroelectric memory device.
Still another object of the present invention is to provide a ferroelectric memory device in which the reference level can easily be changed even after the design phase of the ferroelectric memory device.
A ferroelectric memory device of the present invention comprises: first and second bit lines; a first memory cell transistor; a first ferroelectric capacitor connected to the first bit line through the first memory cell transistor, said first ferroelectric capacitor being included in a first memory cell array; a sense amplifier connected to the first and second bit lines, and having first and second control terminals corresponding to the first and second bit lines; and a offset generating transistor connected between the first and second control terminals, and supplying an offset to the sense amplifier.
According to this structure, by additionally connecting the offset generating transistor between the first and second control terminals of the sense amplifier, the reference level can be generated without the use of a dummy cell. As a result, a high-speed, high-reliability ferroelectric memory device can be provided.
In the above-described ferroelectric memory device, an example of the sense amplifier comprises: a first P-type MOS transistor having its gate connected to the second bit line, its drain connected to the first bit line, and its source connected to the first control terminal; a second P-type MOS transistor having its gate connected to the first bit line, its drain connected to the second bit line, and its source connected to the second control terminal; a first N-type MOS transistor having its gate connected to the second bit line, its drain connected to the first bit line, and its source connected to a third control terminal; and a second N-type MOS transistor having its gate connected to the first bit line, its drain connected to the second bit line, and its source connected to the third control terminal.
Moreover, the offset generating transistor comprises a third P-type MOS transistor having its source and drain connected to the first and second control terminals, and a control signal of the sense amplifier is input to the second control terminal.
According to this structure, the same effects as those of the above-described ferroelectric memory device are produced.
In the above-described ferroelectric memory device, a second example of the sense amplifier comprises: a first P-type MOS transistor having its gate connected to the second bit line, its drain connected to a first data line, and its source connected to the first control terminal; and a second P-type MOS transistor having its gate connected to the first bit line, its drain connected to a second data line, and its source connected to the second control terminal.
Moreover, the offset generating transistor comprises a third P-type MOS transistor having its source and drain connected to the first and second control terminals, and a control signal of the sense amplifier is input to the second control terminal.
According to this structure, the same effects as those of the above-described ferroelectric memory device are produced.
In the above-described ferroelectric memory device, a third example of the sense amplifier comprises: a first N-type MOS transistor having its gate connected to the second bit line, its drain connected to the first bit line, and its source connected to the first control terminal; a second N-type MOS transistor having its gate connected to the first bit line, its drain connected to the second bit line, and its source connected to the second control terminal; a first P-type MOS transistor having its gate connected to the second bit line, its drain connected to the first bit line, and its source connected to a third control terminal; and a second P-type MOS transistor having its gate connected to the first bit line, its drain connected to the second bit line, and its source connected to the third control terminal.
Moreover, the offset generating transistor comprises a third N-type MOS transistor having its source and drain connected to the first and second control terminals, and a control signal of the sense amplifier is input to the second control terminal.
According to this structure, the same effects as those of the above-described ferroelectric memory device are produced.
In the above-described ferroelectric memory device, a fourth example of the sense amplifier comprises: a first N-type MOS transistor having its gate connected to the second bit line, its drain connected to the first data line, and its source connected to the first control terminal; and a second N-type MOS transistor having its gate connected to the first bit line, its drain connected to the second data line, and its source connected to the second control terminal.
Moreover, the offset generating transistor comprises a third N-type MOS transistor having its source and drain connected to the first and second control terminals, and a control signal of the sense amplifier is input to the second control terminal.
According to this structure, the same effects as those of the above-described ferroelectric memory device are produced.
In the ferroelectric memory device having the first or the second example of the sense amplifier, it is preferable to set an offset level Voffset of the sense amplifier by setting a gate potential Vg of the third P-type MOS transistor based on the following relationship:
Voffset=Vgxe2x88x92Vtp
where Vg is the gate potential of the third P-type MOS transistor, Vtp is a threshold voltage of the third P-type MOS transistor, and Voffset is the offset level of the sense amplifier.
According to this structure, since the offset level of the sense amplifier can be set by setting the gate potential of the MOS transistor for offset generation, the reference level can easily be designed in the design phase of the ferroelectric memory device.
In the ferroelectric memory device having the third or the fourth example of the sense amplifier, it is preferable to set an offset level Voffset of the sense amplifier by setting a gate potential Vg of the third N-type MOS transistor based on the following relationship:
Voffset=Vgxe2x88x92Vtnxe2x88x92VDD
where Vg is the gate potential of the third N-type MOS transistor, Vtn is a threshold voltage of the third N-type MOS transistor, Voffset is the offset level of the sense amplifier, and VDD is a power supply voltage.
According to this structure, since the offset level of the sense amplifier can be set by setting the gate potential of the MOS transistor for offset generation, the reference level can easily be designed in the design phase of the ferroelectric memory device.
The ferroelectric memory device having the first or the second example of the sense amplifier may further comprise: an offset control signal generating circuit setting a potential that is input to a gate of the third P-type MOS transistor; and a pad connected to the gate of the third P-type MOS transistor.
According to this structure, by providing the offset control signal generating circuit and the pad, the gate potential of the third P-type MOS transistor can be adjusted. This enables the offset level of the sense amplifier to be adjusted. Consequently, the reference level can easily be changed even after the design phase of the ferroelectric memory device. As a result, a reading operation margin can always be ensured for sample characteristic variations in a case such that the ferroelectric memory device is mass-produced.
In the ferroelectric memory device having the first or the second example of the sense amplifier, a structure having: first and second terminals to which a first predetermined voltage and a second predetermined voltage are applied, respectively; a plurality of resistors connected in series between the first and second terminals; a plurality of fuses connected in parallel to the resistors, respectively; and a third terminal outputting an offset control signal from one of points of connection between the resistors can be considered as a first example of the offset control signal generating circuit.
According to this structure, not only the same effects as those of the above-described ferroelectric memory device having the offset control signal generating circuit and the pad are produced but also the reference level can be adjusted even after the design phase. As a result, a reading operation margin can always be ensured for sample characteristic variations in a case such that the ferroelectric memory device is mass-produced.
In the ferroelectric memory device having the first or the second example of the sense amplifier, a structure having: first and second terminals to which a first predetermined voltage and a second predetermined voltage are applied, respectively; a plurality of resistors connected in series between the first and second terminals; a plurality of switches connected in parallel to the resistors, respectively; a third terminal outputting an offset control signal from one of points of connection between the resistors; a second memory cell array in which setting of the switches is stored; means for reading out data in the second memory cell array, and controlling on/off of the switches; means for writing data into the second memory cell array from outside a chip; and means for reading out data in the second memory cell array, to outside the chip can be considered as a second example of the offset control signal generating circuit.
According to this structure, not only the same effects as those of the above-described ferroelectric memory device having the offset control signal generating circuit and the pad are produced but also the offset level can be set even after the chip is sealed in a package because no fuses requiring cutting are used.
The ferroelectric memory device having the third or the fourth example of the sense amplifier may further comprise: an offset control signal generating circuit setting a potential that is input to a gate of the third N-type MOS transistor; and a pad connected to the gate of the third N-type MOS transistor.
According to this structure, by providing the offset control signal generating circuit and the pad, the gate potential of the third N-type MOS transistor can be adjusted. This enables the offset level of the sense amplifier to be adjusted. Consequently, the reference level can easily be changed even after the design phase of the ferroelectric memory device. As a result, a reading operation margin can always be ensured for sample characteristic variations in a case such that the ferroelectric memory device is mass-produced.
In the ferroelectric memory device having the third or the fourth example of the sense amplifier, a structure having: first and second terminals to which a first predetermined voltage and a second predetermined voltage are applied, respectively; a plurality of resistors connected in series between the first and second terminals; a plurality of fuses connected in parallel to the resistors, respectively; and a third terminal outputting an offset control signal from one of points of connection between the resistors can be considered as a first example of the offset control signal generating circuit.
According to this structure, not only the same effects as those of the above-described ferroelectric memory device having the offset control signal generating circuit and the pad are produced but also the reference level can be adjusted even after the design phase. As a result, a reading operation margin can always be ensured for sample characteristic variations in a case such that the ferroelectric memory device is mass-produced.
In the ferroelectric memory device having the third or the fourth example of the sense amplifier, a structure having: first and second terminals to which a first predetermined voltage and a second predetermined voltage are applied, respectively; a plurality of resistors connected in series between the first and second terminals; a plurality of switches connected in parallel to the resistors, respectively; a third terminal outputting an offset control signal from one of points of connection between the resistors; a second memory cell array in which setting of the switches is stored; means for reading out data in the second memory cell array, and controlling on/off of the switches; means for writing data into the second memory cell array from outside a chip; and means for reading out data in the second memory cell array, to outside the chip can be considered as a second example of the offset control signal generating circuit.
According to this structure, not only the same effects as those of the above-described ferroelectric memory device having the offset control signal generating circuit and the pad are produced but also the offset level can be set even after the chip is sealed in a package because no fuses requiring cutting are used.
In the ferroelectric memory device having the first, the second, the third or the fourth example of the sense amplifier, a structure having means for precharging the first and second control terminals to a predetermined voltage may be adopted.
According to this structure, by providing the precharging circuit, the control terminals of the sense amplifier can be precharged with reliability. As a result, the reading operation can more accurately be performed.
The above-described ferroelectric memory device may further comprise: a second memory cell transistor; a second ferroelectric capacitor connected to the second bit line through the second memory cell transistor, said second ferroelectric capacitor being included in the first memory cell array; and a selecting circuit connecting a control signal of the sense amplifier to the second control terminal when data in the first ferroelectric capacitor is read out, and connecting the control signal of the sense amplifier to the first control terminal when data in the second ferroelectric capacitor is read out.
According to this structure, by providing the selecting circuit, data can be read out not only onto the first bit line but also onto the second bit line by connecting the second memory cell transistor and the second ferroelectric capacitor. As a result, a denser memory cell array can be structured.